1. Field of the Invention
The present invention relates to data storage access circuits in high-speed CMOS pipeline architecture in general and in particular to a method and apparatus comprising a CMOS pipeline buffer with means for selectively switching the buffer between asynchronous and synchronous modes of operation for use in both low and high powered applications of such architecture.
2. Description of the Prior Art
Conventional high speed pipeline memory access circuits such as used in desk top video graphics systems, color palettes, and the like, require complementary synchronized clocks to control the gates of the internal flip-flops used to latch decoded addresses for addressing memory cells, storage registers or other data storage devices used therein. Such circuits, which typically have clock rates in excess of 80 mHz, i.e. periods of less than 12 nsec., will not provide memory or register access while the clock is disabled. This limitation in the prior known circuits generally prevents their use in low power applications and in particular has prevented low power asynchronous accessing of memory circuits in such low power applications by external devices.